Many integrated circuits facilitate defect identification using Built-In Self Test (BIST) mechanisms. The term “BIST” can refer to testing techniques in which parts of a circuit (chip, board, or system) are used to test the circuit itself. BIST circuits may be formed directly on the same chip when forming the integrated circuits and other circuit components that require testing. Such BIST schemes may be used during wafer level manufacturing test to screen out defects. Alternatively, BIST schemes may be used after each power-on to conduct self-checking of the circuits. The term “ABIST,” can mean “Array BIST,” or a BIST system designed to test an embedded memory device. Testing multi-port memory (e.g., Processor internal Register Memory Array) may present complications, such as how to fully test port interactions without necessitating large amounts of extra test-only hardware. Multi-port memory may be tested using a micro-architecture specific program such as an Architectural Verification Program (AVP). An AVP may be any software or firmware program that is intended to execute in a chip to verify architected functions of the chip. In the case of multi-port memories, an AVP may be designed to fully verify a particular embedded memory. However, if the memory is later embedded in a different chip or has a slightly different implementation, the AVP program must be changed. In addition, the AVP is generally developed late in the design process, typically after the hardware is developed, and it is a complex process to test memory array cell characteristics. Since creating and maintaining such AVP programs can be labor-intensive and burdensome, it is difficult to accomplish this late in the design process without causing schedule or quality slippage.
Implementing an ABIST system may require using valuable chip area to incorporate ABIST hardware. Accordingly, to optimize an ABIST scheme, it may be desirable to reduce the amount of “test-only” hardware needed by an ABIST system. Test-only hardware may be considered any hardware unnecessary for normal functionality but necessary for ABIST testing. Such test-only hardware occupies valuable space on a chip and should be minimized. Optimizing an ABIST system may also require testing at speeds that simulate functional conditions and exercise the dynamic characteristics of memory circuits. Additionally, scanned ABIST testing of consecutive reads, consecutive read/write, or consecutive writes of a memory typically requires additional logic configured as a set of shadow latches for addressing.
In summary, an invention is needed that allows scanned memory ABIST testing of multi-ported memory arrays at functional speeds, while minimizing the amount of test-only hardware needed for ABIST testing and reducing the potential for schedule slippage.